A need continues to grow for more complex semiconductor (SC) devices and circuits able to operate at higher and higher frequencies and handle increasing amounts of power and have lower unit cost. Many of these requirements create conflicting demands on semiconductor device and integrated circuit (IC) design and manufacturing technology. For example, and not intended to be limiting, most SC devices and ICs are fabricated in and/or on substrate wafers, usually but not always single crystal SC wafers, which are then cut up (“singulated”) into the individual devices or ICs. The manufacturing cost can be reduced by using larger and larger wafers, since more individual devices and ICs can be produced at the same time on larger wafers. However, to avoid undue wafer breakage, the wafer thickness must generally be increased as the wafer diameter is increased.
If only one surface of the SC die or IC is available for fabricating devices and connections, the desired degree of complexity may not be achievable with present day structures and fabrication techniques. Further, as operating speed, power handling and wafer thickness increase, efficient heat removal from the resulting device or IC becomes more and more difficult. Thus, there is a strong desire to provide electrically and thermally conductive connections between the front and rear surfaces of the devices or ICs and to minimize the device and/or IC substrate thickness, without compromising mechanical robustness of the wafers during manufacture.
It is known to use conductor filled vias through SC wafers as a means of providing electrical and thermal connections between the front and rear surfaces of the wafer and resulting individual devices and IC die. These conductor filled vias are referred to as “through-substrate-vias” or “through-semiconductor-vias” and abbreviated as “TSV” (singular) or “TSVs” (plural). However, the desire to use larger diameter and therefore thicker wafers for cost efficient manufacturing and at the same time to provide highly conductive TSVs for electrically and/or thermally coupling the front and rear faces of the wafer and resulting die are in conflict. The thicker the wafers, the more difficult it is to etch and fill narrow TSVs with conductors. However, if the vias are made larger, then greater wafer and die surface area must be devoted to such vias. In the prior art, thicker wafers have generally required larger area TSVs consuming greater device and IC surface area, thereby lowering the device and IC packing density on the wafer and increasing the device and IC manufacturing cost. Trying to use large diameter thin wafers so as to maintain the device area packing density reduces the mechanical stability of the wafers. It is well known that thin wafers break more easily during device and IC processing, thereby reducing the manufacturing yield and increasing the cost of the finished devices and ICs. Thus, a need continues to exist for improved SC device and IC structures and fabrication techniques that can provide minimal area TSVs for front-side-to-back-side interconnections and thin device or IC substrates for efficient heat removal, without significantly compromising mechanical stability of the wafers during manufacturing.